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Book Information
76 pages • paperback • 1 edition
ISBN/UID: 9783659180767
Format: Paperback
Language: English
Publisher: LAP Lambert Academic Publishing
Edition Pub Date: 18 Jul 2012
Description
The book investigates test vector reordering algorithm for minimizing the power dissipation during testing of VLSI circuits. Testing plays a key role in design flow and is the major challenging task for design and test engineers. Power dissipation...
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Content Warnings
76 pages • paperback
ISBN/UID: 9783659180767
Format: Paperback
Language: English
Publisher: LAP Lambert Academic Publishing
Edition Pub Date: 18 Jul 2012
Description
The book investigates test vector reordering algorithm for minimizing the power dissipation during testing of VLSI circuits. Testing plays a key role in design flow and is the major challenging task for design and test engineers. Power dissipation...
Community Reviews
Content Warnings