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156 pages • missing pub info (view editions)
ISBN/UID: 9783659171192
Format: Paperback
Language: English
Publisher: LAP Lambert Academic Publishing
Edition Pub Date: 10 July 2012
Description
Low power, high speed binary multiplier is an essential component of digital computers. Many architectures of multiplier based on Booth multiplication and array multiplication algorithms have been implemented. The array multiplier using Wallace tr...
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156 pages • missing pub info (view editions)
ISBN/UID: 9783659171192
Format: Paperback
Language: English
Publisher: LAP Lambert Academic Publishing
Edition Pub Date: 10 July 2012
Description
Low power, high speed binary multiplier is an essential component of digital computers. Many architectures of multiplier based on Booth multiplication and array multiplication algorithms have been implemented. The array multiplier using Wallace tr...